Using Queues in VHDL with VUnit
In this post we will discuss what queues are and how we can use them in VHDL with the VUnit verification framework.
tag: Verification
Setting up a VHDL Verification Environment with VUnit
In this post we will set up a minimal verification environment with VUnit. Our testbench will include verification components for driving an monitoring an AXI-Stream bus.
‘Hello World’ with the Vitis Unified IDE and the Zynq 7000
In this post we will create and run a ‘Hello World’ program on the Zynq 7000 SoC using the Vitis Unified IDE.
Minimal UVVM Verification Environment
In this post we will set up a minimal example of a VHDL verification environment using the UVVM Verification Framework.
AXI4-Stream Slave with UVVM Light
In this post we will expand our minimal UVVM test bench to include an AXI-Stream Slave interface that receives and validates the data sent by an AXI-Stream Master.
AXI4-Stream Master with UVVM Light
In this post we will set up a minimal testbench to generate data using an AXI4-Stream Master Bus Functional Model from the UVVM Light library.