All Things FPGA.

Welcome to Elaborated Designs, a website that explores all things related to FPGA design and verification, digital signal processing, and embedded systems.

I’m Isaac, an FPGA developer in Germany. In my day job I design digital systems and embedded software for industrial applications.

Thanks a lot for stopping by. I hope you find these resources useful.

Setting up a VHDL Verification Environment with VUnit

In this post we will set up a minimal verification environment with VUnit. Our testbench will include verification components for driving an monitoring an AXI-Stream bus.